Shahid Beheshti University
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Last Update: 2018/02/12
Ghassem Jaberipur
Professor

Faculty: Computer Engineering and Science
Department:
Phone: 29904165
Email: jaberipur@sbu.ac.ir
Personal website: http://facultymembers.sbu.ac.ir/jaberipur/

Academic Degrees

PhD, , Sharif University of Technology, Tehran, 2004.


Journal Articles
1. S. Amanollahi baharvand, G. Jaberipur, "Fast Energy Efficient Radix-16 Sequential Multiplier" , IEEE Embedded Systems Letters, pp.1-1, 2017.
2. S. G., G. Jaberipur, "Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication" , IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol.25, pp.75-86, 2017.
3. S. Amanollahi baharvand, G. Jaberipur, "Energy Efficient VLSI Realization of Binary64 Division with Redundant Number Systems" , IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol.25, pp.954-961, 2017.
4. A. Hosseiny, G. Jaberipur, "Decimal Goldschmidt A hardware algorithm for radix-10 division" , COMPUTERS and ELECTRICAL ENGINEERING, Vol.53, pp.40-55, 2016.
5. A. Hosseiny, G. Jaberipur, "Decimal Square Root Algorithm and Hardware Implementation" , CIRCUITS SYSTEMS AND SIGNAL PROCESSING, Vol.35, pp.4195-4219, 2016.
6. H. Ghasemi motlagh, G. Jaberipur, "The Impact of Excess-Modulo Representation of Residues on Modulo- (2 n-5) Parallel Prefix Addition" , The csi journal of computer science and engineering, Vol.13, pp.48-53, 2016.
7. S. Amanollahi baharvand, G. Jaberipur, "Architecture-Level Design Space Exploration for Radix-16 Sequential Multipliers" , The csi journal of computer science and engineering, Vol.7, pp.24-30, 2016.
8. Z. Torabi, G. Jaberipur, "Fast low energy RNS comparators for 4-moduli sets 2n 1 2n m with m 2n 1 1 2n 1 1" , INTEGRATION-THE VLSI JOURNAL, Vol.55, pp.155-161, 2016.
9. Z. Torabi, G. Jaberipur, "Low-Power/Cost RNS Comparison via Partitioning the Dynamic Range" , IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol.24, pp.1849-1857, 2016.
10. M. D., G. Jaberipur, "Conditional Speculative Mixed Decimal/Binary Adders via Binary-Coded-Chiliad Encoding" , COMPUTERS and ELECTRICAL ENGINEERING, Vol.50, pp.39-53, 2016.
11. D. Abedi, G. Jaberipur, M. S., "Coplanar Full Adder in Quantum-Dot Cellular Automata via Clock-Zone Based Crossover" , IEEE TRANSACTIONS ON NANOTECHNOLOGY, Vol.14, pp.497-504, 2015.
12. G. Jaberipur, S. Fatemi langeroodi, "(4 2log n) G Parallel Prefix Modulo-(2n 3)Adder via Double Representationof Residues in 0 2" , IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Vol.62, pp.583-587, 2015.
13. H. Ahmadifar, G. Jaberipur, "A New Residue Number System with 5-Moduli Set 2 2q 2 q 3 2 q 1" , COMPUTER JOURNAL, Vol.58, pp.1548-1565, 2015.
14. S. Fatemi langeroodi, G. Jaberipur, "(4 2 log n ) G Parallel Prefix Modulo- (2 n-3) Adder via Double Representation of Residues in 0 2" , COMPUTERS and ELECTRICAL ENGINEERING, Vol.62, pp.583-587, 2015.
15. S. G., G. Jaberipur, "Comment on High Speed Parallel Decimal Multiplication with Redundant Internal Encodings" , IEEE TRANSACTIONS ON COMPUTERS, Vol.64, pp.293-294, 2015.
16. A. Pishvaie, G. Jaberipur, A. Jahanian, "High Performance CMOS (4 2) Compressors" , INTERNATIONAL JOURNAL OF ELECTRONICS, Vol.101, pp.1511-1525, 2014.
17. M. D., G. Jaberipur, "Low Area/Power Decimal Addition with Carry-Select Correction and Carry-Select Sum-digits" , INTEGRATION-THE VLSI JOURNAL, Vol.47, pp.443-451, 2014.
18. S. Gorgin, G. Jaberipur, R. Hashemi asl, "Efficient ASIC and FPGA Implementation of Binary-Coded Decimal Digit Multipliers" , CIRCUITS SYSTEMS AND SIGNAL PROCESSING, Vol.33, pp.3883-3899, 2014.
19. A. P., G. Jaberipur, A. Jahanian, "High Performance CMOS (4 2) Compressors" , Taylor Francis, 2014.
20. A. P., G. Jaberipur, A. Jahanian, "Redesigned CMOS (4 2) compressor for fast binary multipliers" , CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING-REVUE CANADIENNE DE GENIE ELECTRIQUE ET INFORMATIQUE, Vol.36, pp.111-115, 2014.
21. G. Jaberipur, H. Ahmadifar, "A ROM-less Reverse RNS Converter for Moduli Set 2 q 1 2 q 3" , IET Computers and Digital Techniques, Vol.1, pp.11-22, 2014.
22. G. Jaberipur, M. D., "Ambiguity-resolving Syntax Definition with Asserted Shift Reduce Sets" , Scientia Iranica, Vol.20, pp.1939-1952, 2013.
23. G. Jaberipur, B. Parhami, "Efficient Realization of Arithmetic Algorithms with Weighted Collections of Posibits and Negabits" , IET Computers and Digital Techniques, Vol.6, pp.259-268, 2012.
24. P. A., G. Jaberipur, A. Jahanian, "Improved CMOS (4 2) compressor designs for parallel multipliers" , COMPUTERS and ELECTRICAL ENGINEERING, Vol.38, pp.1703-1716, 2012.
25. A. Keyvani, A. Hosseiny, G. Jaberipur, "Improving the Speed of Decimal Division" , IET Computers and Digital Techniques, Vol.5, pp.393-404, 2011.
26. A. Keyvani, G. Jaberipur, "Decimal CORDIC Rotation based on Selection by Rounding" , COMPUTER JOURNAL, Vol.54, pp.1798-1809, 2011.
27. G. Jaberipur, "A Generic Modulo 2 n-1 Adder Based on Stored Negabit Representation of Residues" , The csi journal of computer science and engineering, Vol.6, pp.29-35, 2011.
28. G. Jaberipur, B. Parhami, S. G., "REDUNDANT-DIGIT FLOATING-POINT ADDITION SCHEME BASED ON A STORED ROUNDING VALUE" , IEEE TRANSACTIONS ON COMPUTERS, Vol.59, pp.694-706, 2010.
29. S. G., G. Jaberipur, "DESIGN AND SYNTHESIS OF HIGH SPEED LOW POWER SIGNED DIGIT ADDERS" , Journal of iranian association of electrical and electronics engineering, Vol.7, pp.7-14, 2010.
30. G. Jaberipur, S. G., "An improved maximally redundant signed digit adder" , COMPUTERS and ELECTRICAL ENGINEERING, Vol.36, pp.491-502, 2010.
31. G. Jaberipur, "Fully erdundant decimal addition and subtraction using stored unibit encoding" , INTEGRATION-THE VLSI JOURNAL, Vol.43, pp.34-41, 2009.
32. G. Jaberipur, "Improving the sped of parallel decimal multiplication" , IEEE TRANSACTIONS ON COMPUTERS, Vol.58, 2009.
33. S. Gorgin, G. Jaberipur, "A fully redundant decimal adder and its applicaionin parallel decimal multipliers" , Microelectronic Journal, Vol.40, pp.147-1481, 2009.
34. G. Jaberipur, B. Parhami, "Constant-Time Addition with Hybrid-Redundant Numbers Theory and Implementations" , INTEGRATION-THE VLSI JOURNAL, pp.49-64, 2008.
35. G. Jaberipur, A. Keyvani, "Binary-Coded Decimal (BCD) Digit-Multipliers" , IET Computers and Digital Techniques, Vol.1, pp.377-381, 2007.
36. G. Jaberipur, B. Parhami, "Stored-Transfer Representations with Weighted Digit-Set Encodings for Ultrahigh-Speed Arithmetic" , IET CIRCUITS DEVICES AND SYSTEMS, Vol.1, pp.102-110, 2007.
37. G. Jaberipur, B. Parhami, M. Ghodsi, "An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding" , Springer Science-Journal of VLSI Signal Processing, Vol.42, pp.149-158, 2006.
38. G. Jaberipur, B. Parhami, M. Ghodsi, "Weighted Two-Valued Digit-Set Encodings Unifying Efficient Hardware Representation Schemes for Redundant Number Systems" , IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, Vol.52, pp.1348-1357, 2005.
39. G. Jaberipur, M. Ghodsi, "High Radix Signed Digit Number Systems Representation Paradigms" , Scientia Iranica, Vol.10, pp.383-391, 2003.
40. ق. جابري پور, "پردازش كارآ نياز اساسي استاندارد كردن رمز تبادل اطلاعات فارسي" , گزارش كامپيوتر, صفحات:19-19, 1364.
41. ق. جابري پور, "يك راه حل ساده براي مرتب كردن اطلاعات فارسي" , گزارش كامپيوتر, 1363.
42. ق. جابري پور, "فارسي سازي زبانهاي برنامه سازي" , گزارش كامپيوتر, 1985.


Conference Articles
1. H. Ahmadifar, GH. Jaberipoor, "Improved modulo-(2 n 3) multipliers" , In 17th CSI International symposium on Computer Architecture and Digital Systems (CADS2013), 2013.
2. P. A., GH. Jaberipoor, A. Jahanian, "Redesigned CMOS (4 2) compressor for fast binary multipliers" , In ICEE2012, 2012.
3. S. Emami, M. D., GH. Jaberipoor, "Radix-10 addition with Radix-1000 encoding of decimal operands" , In The 16th CSI international symposium on computer architecture and digital systems (cads), 2012.
4. GH. Jaberipoor, B. Parhami, M. Ghodsi, "A Class of Stored-Transfer Representations for Redundant Number Systems" , In 35th Asilomar Conf. Signals Systems and Computers, 2011.
5. GH. Jaberipoor, B. Parhami, S. Nejati, "On Building General Modular Adders from Standard Binary Arithmetic Components" , In 35th Asilomar Conf. Signals Systems and Computers, 2011.
6. GH. Jaberipoor, S. Nejati, "Balanced minimal latency RNS addition for moduli set 2 n-1 2 n 2 n 1" , In 18th international conference on systems signals and image processing, 2011.
7. S. G., GH. Jaberipoor, "A Family of High Radix Signed Digit Addres" , In The 20th ieee symposiumon computer arithmetic, 2011.
8. S. G., GH. Jaberipoor, "A Family of Signed Digit Adders" , In The 20th ieee symposiumon computer arithmetic, 2011.
9. GH. Jaberipoor, "A Modulo 2n 1 Multiplier with Double-LSB Encoding of residues" , In The 15th CSI international symposium on computer architecture and digital systems (cads), 2010.
10. GH. Jaberipoor, B. Parhami, "Posibits Negabits and Their Mixed Use in Efficient Realization of Arithmetic Algorithms" , In The 15th CSI international symposium on computer architecture and digital systems (cads), 2010.
11. GH. Jaberipoor, B. P., "Unified approach to the deaign of modulo (2 1) adderes based on signed lsb represention of residues" , In Ieee arith 19, 2009.
12. S. G., GH. Jaberipoor, "Fully redundant decimal arithmetic" , In Ieee arith 19, 2009.
13. S. G., GH. Jaberipoor, B. Parhami, "Design and evaluation of decimal array multipliers" , In Ieee arith 19, 2009.
14. GH. Jaberipoor, S. G., "A high speed low power signed digit adder" , In 16th Iranian conference on electrical engineering ICEE 2008, 2008.
15. GH. Jaberipoor, "A Nonspeculative One-Step Maximally Redundant Signed Digit Adder" , In CSICC 2008, 2008.
16. GH. Jaberipoor, B. Parhami, M. Ghodsi, "Weighted Bit-Set Encodings for Redundant Digit Sets Theory and Applications pp. 1629-1633 November 2002." , In 36th Asilomar Conf. Signals Systems and Computers, 2002.
17. ع. پيشوايي, ق. جابري پور, ع. جهانيان, "طراحي كمپرسور (2 4 CMOS سريع بر پايه دروازه XOR سه ورودي" هفدهمين كنفرانس ملي سالانه انجمن كامپيوتر ايران, 1390.
18. ق. جابري پور, "SADL زبان توصيف آرايه هاي تپنده" , 1377.


Shahid Beheshti University

Shahid Beheshti University