Shahid Beheshti University
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Last Update: 2018/02/12
Ali Jahanian
Associate professor

Faculty: Computer Engineering and Science
Department:
Phone: 29904188
Email: jahanian@sbu.ac.ir
Personal website: http://facultymembers.sbu.ac.ir/jahanian/

Academic Degrees

PhD, , Amirkabir University of Technology, Tehran.


Journal Articles
1. M. Taajoban, A. Jahanian, "Improved Experimental Time of Ultra0large Bioassays using a Parallelized Microfluidic Biochip Architecture/Scheduling" , IET Nanobiotechnology, 2017.
2. Z. Beiki, A. Jahanian, "DENA A Configurable Micro-architecture and Design Flow for Bio-medical DNA-based Logic Design" , IEEE Transactions on Biomedical Circuits and Systems, pp.1-10, 2017.
3. A. Belghadr, A. Jahanian, "Three-dimensional Physical Design Flow for Monolithic 3D-FPGAs to Improve Timing Closure and Chip Area Systems" , JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, Vol.26, pp.1750154-1-1750154-25, 2017.
4. S. Farhadtoosky, A. Jahanian, "Customized Placement Algorithm of Nanoscale DNA Logic Circuits" , JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, Vol.26, pp.1750150-1-1750150-14, 2017.
5. M. T., A. Jahanian, "Higher Flexibililty of Reconfigurable Digital Micro/Nano Fluidic Biochips using an FPGA-Inspired Architecture" , Scientia Iranica, Vol.23, pp.1554-1562, 2016.
6. S. Zamanzadeh, A. Jahanian, "ASIC Design Protection against Reverse Engineering during the Fabrication Process using Automatic Netlist Obfuscation Design Flow" , Isecure, The Isc International Journal Of Information Security, Vol.8, pp.87-98, 2016.
7. S. Zamanzadeh, A. Jahanian, "Higher Security of ASIC Fabrication Process Against Reverse Engineering Attack using Automatic Netlist Encryption Methodology" , MICROPROCESSORS AND MICROSYSTEMS, Vol.42, pp.1-9, 2016.
8. S. Zamanzadeh, A. Jahanian, "Security Path an Emerging Design Methodology to Protect the FPGA IPs against Passive/Active Design Tampering" , JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, Vol.32, pp.329-343, 2016.
9. S. Zamanzadeh, A. Jahanian, "Self Authentication Path Insertion in FPGA-based Design Flow for Tamper-resistant Purpose" , Isecure, The Isc International Journal Of Information Security, Vol.8, pp.53-60, 2016.
10. S. Daryanavard, M. Eshghi, A. Jahanian, "Acceleration of Inter-Task Routing for JIT Compilation Reconfigurable Computing Platform Using Customized Processor" , International Review on Computers and Software, Vol.10, pp.380-391, 2015.
11. M. Vosoughi, A. Jahanian, "Security-aware Register Placement to Hinder Malicious Hardware Updating and Improve Trojan Detectability" , Isesco journal of science and technology, Vol.7, pp.1-7, 2015.
12. M. Morshedzadeh, A. Jahanian, P. Poor ashraf, "Three-dimensional Switchbox Multiplexing in Emerging 3D-FPGAs to Reduce Chip Footprint and Improve TSV Usage" , INTEGRATION-THE VLSI JOURNAL, Vol.50, pp.81-90, 2015.
13. A. Pishvaie, G. Jaberipur, A. Jahanian, "High Performance CMOS (4 2) Compressors" , INTERNATIONAL JOURNAL OF ELECTRONICS, Vol.101, pp.1511-1525, 2014.
14. S. Daryanavard, M. Eshghi, A. Jahanian, "A Fast Placement Algorithm for Embedded Just-In-Time Reconfigurable Extensible Processing Platform" , JOURNAL OF SUPERCOMPUTING, Vol.71, pp.121-143, 2014.
15. A. P., G. Jaberipur, A. Jahanian, "High Performance CMOS (4 2) Compressors" , Taylor Francis, 2014.
16. A. P., G. Jaberipur, A. Jahanian, "Redesigned CMOS (4 2) compressor for fast binary multipliers" , CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING-REVUE CANADIENNE DE GENIE ELECTRIQUE ET INFORMATIQUE, Vol.36, pp.111-115, 2014.
17. A. Belghadr, A. Jahanian, "Metro-on-FPGA a feasible solution to improve the congestion and routing resource management in future FPGAs" , INTEGRATION-THE VLSI JOURNAL, Vol.47, pp.96-104, 2014.
18. Z. M., A. Jahanian, "Improved Delay and Process Variation Tolerance of Clock Tree Network in Ultra-large Circuits using Hybrid RF/Metal Clock Routing" , JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, Vol.23, pp.1-19, 2014.
19. A. Bakhshizadeh, A. Jahanian, "Trojan Vulnerability Map an Efficient Metric for Modeling and Improvement of Hardware Security Level" , IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Vol.95, pp.1-9, 2012.
20. A. Belghadr, A. Jahanian, "Performance Improvement and Congestion Reduction of Large FPGAs using On-chip Microwave Interconnects" , IEICE TRANSACTIONS ON COMMUNICATIONS, Vol.95, pp.1610-1618, 2012.
21. A. Jahanian, R. Abdollahi, "Improved Timing Closure by Analytical Buffer and TSV Planning in Three-dimensional Chips" , IEICE ELECTRONICS EXPRESS (), Vol.9, pp.1849-1854, 2012.
22. P. A., G. Jaberipur, A. Jahanian, "Improved CMOS (4 2) compressor designs for parallel multipliers" , COMPUTERS and ELECTRICAL ENGINEERING, Vol.38, pp.1703-1716, 2012.
23. Y. Zare khafri, A. Jahanian, "Improved Line Tracking System for Autonomous Navigation of" , INTERNATIONAL JOURNAL OF ROBOTICS and AUTOMATION, Vol.30, pp.25-30, 2012.
24. A. F., A. Jahanian, "Parallelizing the FPGA Global Routing Algorithm on Multi-core Systems without Quality Degradation" , IEICE ELECTRONICS EXPRESS (), Vol.24, pp.2061-2067, 2011.
25. A. Jahanian, M. S., "Using chip master planning in automatic ASIC design flow to improve performance and buffer resource management" , Journal of computer and robotics, pp.125-135, 2011.
26. M. Moayeri, A. Jahanian, P. Navi, "Comparative Performance Evaluation of Large FPGAs with CNFET- and CMOS-based Switches in Nanoscale" , JOURNAL NANO MICRO LETTERS, Vol.3, pp.177-178, 2011.
27. A. Jahanian, M. Saheb zamani, H. Safizadeh, "Improved predictability timing yield and power consumption using hierarchical highways-on-chip planning methodology" , INTEGRATION-THE VLSI JOURNAL, Vol.44, pp.123-135, 2011.
28. M. Moayeri, A. Jahanian, K. Navi, "Comparative Performance Evaluation of Large FPGAs with CNFET- and CMOS based Switches in Nanoscale" , JOURNAL NANO MICRO LETTERS, Vol.3, 2011.
29. A. Jahanian, M. Saheb zamani, "Early buffer planning with congestion control using buffer requirement map" , JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, Vol.5, pp.949-973, 2010.
30. A. Jahanian, M. S., M. Rezvani, "An Improved Standard Cell Placement Methodology using Hybrid Analytic and Heuristic Techniques" , ADVANCES IN COMPUTER SCIENCE AND ENGINEERING, Vol.6, 2009.
31. A. Jahanian, M. Saheb zamani, "Higher routability and reduced crosstalk noise by asynchronous multiplexing of on-chip interconnects" , Scientia Iranica, Vol.17, 2009.
32. M. Sanjabi, S. Maabi, A. Jahanian, S. Khalighi, "A Landmark-based Navigation System for High Speed Cars in the Roads with Branches" , International Journal of Information Acquisition (IJIA), Vol.6, pp.193-202, 2009.
33. A. Jahanian, M. Rezvani, M. Saheb zamani, M. Najibi, "Evaluating the Metro-on-Chip Methodology to Improve the Congestion and Routability" , Advances in Computer and Information Sciences and Engineering, pp.689-696, 2008.
34. A. Jahanian, M. Saheb zamani, "Using metro-on-chip in physical design flow for congestion and routability improvement" , MICROELECTRONICS JOURNAL, Vol.39, pp.261-274, 2008.
35. A. Jahanian, M. Saheb zamani, "Metro-on-Chip an efficient physical design technique for congestion reduction" , IEICE ELECTRONICS EXPRESS (), Vol.4, pp.510-516, 2007.
36. M. Saeedi, A. Jahanian, M. Saheb zamani, "Evaluation prediction and reduction of routing congestion" , MICROELECTRONICS JOURNAL, Vol.38, pp.942-958, 2007.
37. ط. يحيي, ش. زارع كاريزي, ع. جهانيان, "بررسي ميزان بيان miRNA جهت تشخيص زودهنگام سرطان با استفاده از دروازه هاي منطقي DNA" , مجله دانشگاه علوم پزشكي اراك، فصلنامه ره آورد دانش, نسخه 9, صفحات:96-109, 1396.
38. ز. علي محمد , ع. جهانيان, "طرح ريزي اتصالات امواج راديويي روي مدارهاي مجتمع خاص منظوره با هدف بهبود" , نسخه 9, صفحات:34-41, 1390.
39. ع. جهانيان, م. صاحب الزماني, "توزيع مناسب منابع بافر با طرح ريزي بافرها در سطح جاسازي با هدف كاهش تعداد بافر و مديريت تراكم" , نسخه 5, صفحات:12-22, 1386.


Conference Articles
1. H. Hossein talaee, A. Jahanian, "Layout Vulnerability Reduction against Trojan Insertion using Security-aware White Space Distribution" , In International Symposium on VLSI (ISVLSI), 2017.
2. M. Sanjabi, A. Jahanian, M. T., "High-Performance General-Purpose Arithmetic Operations using the Massive Parallel DNA-based Computation" , In EuroMicro Digital System Design (DSD2017), 2017.
3. S. Zamanzadeh, A. Jahanian, "Scalable Security Path Methodology A Cost-security Trade-off to Protect FPGA IPs against Active and Passive Tampers" , In Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 2017.
4. P. Talebian, A. Jahanian, "Isolating the Register-bank Trojans in General-purpose Microprocessors using Secure Programming" , In 1st International Conference on New Research Achievements in Electrical and Computer Engineering, 2016.
5. S. Farhadtoosky, A. Jahanian, "A new Cell Placement Algorithm for Localized DNA Logic Circuits Mounted on Origami Surface" , In International Conference on DNA Computing and Molecular Programming (DNA22), 2016.
6. S. Zamanzadeh, A. Jahanian, "Security Improvement of FPGA Configuration File Against the Reverse Engineering Attack" , In 13th International ISC Conference on Information Security and Cryptology (ISCISC 2016), 2016.
7. A. Abdoli, A. Jahanian, "Fault-tolerant architecture and CAD algorithm for field-programmable pin-constrained digital microfluidic biochips" , In CSI Symposium on Real-Time and Embedded Systems and Technologies (RTEST), 2015.
8. S. Daryanavard, M. Eshghi, A. Jahanian, "Design of CAD ASIP for JIT extensible processor Case study on PathFinder routing algorithm" , In 23rd Iranian Conference on Electerical Engineering, 2015.
9. Z. Beiki, A. Jahanian, "DENA a Configurable Architecture for Multi-stage DNA Logic Circuit Design" , In International Conference on DNA Computing and Molecular Programming (DNA21), 2015.
10. A. Jahanian, "Design of CAD ASIP for JIT extensible processor case study on Simulated Annealing placer" , In I, 2014.
11. A. Hosseiny, S. Amanollahi baharvand, A. Jahanian, "Improved performance and resource usage of FPGA using resource-aware design the case of decimal array multiplier" , In International Symposium on Computer Architecture and digital systems ( CADS ), 2013.
12. A. Jahanian, "A General-Purpose Field-Programmable Pin-Constrained Digital Microfluidic Biochip" , In International Symposium on Computer Architecture and digital systems ( CADS ), 2013.
13. A. Zarei, A. Jahanian, "RF resource planning in application specific integrated circuits to improve timing closure" , In International Symposium on Computer Architecture and digital systems ( CADS ), 2013.
14. A. F., A. Jahanian, "A new nanowire-based FPGA to improve routing congestion and routability" , In Sharif Conference on Future Electronics, 2013.
15. Z. M., A. Jahanian, "Clock tree network using hybrid RF/metal clock routing" , In Sharif Conference on Future Electronics, 2013.
16. A. Jahanian, B. Poorshirazi, "RF-Interconnect resource assignment and placement algorithms in application specific ICs to improve performance and reduce routing congestion" , In Euromicro conference on digital system design, 2012.
17. A. Malekpoor, M. S., A. Jahanian, "Design implementation and improvement of decimal parallel multiplier on ASIC and FPGA" , In ICEE2012, 2012.
18. F. KH., A. Jahanian, "Improved performance and power consumption of three-dimensional FPGAs using Carbon Nanotube interconnects" , In International Symposium on Computer Architecture and Digital Systems (CADS), 2012.
19. M. Morshedzadeh, A. Jahanian, "Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usage" , In Great Lakes Symposium on VLSI (GLSVLSI)(2012), 2012.
20. M. N., A. Jahanian, H. Zarandi, "Modeling evaluation and mitigation of SEU error in three-dimensional FPGAs" , In International Symposium on Computer Architecture and Digital Systems (CADS), 2012.
21. M. S., A. Jahanian, S. Amanollahi baharvand, N. Niralaee, "ParSA parallel simulated annealing placement algorithm for multi-core systems" , In International Symposium on Computer Architecture and Digital Systems (CADS), 2012.
22. P. A., GH. Jaberipoor, A. Jahanian, "Redesigned CMOS (4 2) compressor for fast binary multipliers" , In ICEE2012, 2012.
23. S. Marashi, A. Jahanian, "TrueFlex A Flexible and Efficient Evaluation Platform for Networked Automotive Systems" , In ICEE2012, 2012.
24. S. Talebi, N. Abolghasemi, A. Jahanian, "EJOP an extensible Java processor with reasonable performance/flexibility trade-off" , In EuroMicro Digital System Design(DSD), 2012.
25. A. Jahanian, S. Amanollahi baharvand, "Edu3 a simple and efficient platform for education of three-dimensional physical design automation algorithms" , In Design Automation and test(Date), 2012.
26. A. Jahanian, S. Amanollahi baharvand, "EduCAD an Efficient Flexible and Easily Revisable Physical Design Tool for Educational Purposes" , In Design Automation and test(Date), 2012.
27. B. Salami, M. S., A. Jahanian, S. Khalighi, "Landmark-based car navigation with overtake capability in multi-agent environments" , In 4th ICAART, 2012.
28. A. D., A. Jahanian, A. Mehrshahi, M. Teimoori, "Feasibility study of using the rf interconects in large fpgas to improve routing tracks usage" , In 2011IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, 2011.
29. B. Salami, M. S., A. Jahanian, "VMAP a variation map-aware placement algorithm for leakage power reduction in FPGAs" , In 14th euromicro conference on Digital System Design(DSD), 2011.
30. M. Alipor, M. S., A. Jahanian, "Congestion and Track Usage Improvement of Large FPGAs Using Metro-on-FPGA Methodology" , In Great Lakes Symposium on VLSI (GLSVLSI) (2011 ), 2011.
31. M. Malekshahi, A. Jahanian, "A CNT/Metal Hybrid Routing Architecture to Improve Performance of Ultra-Large FPGAs" , In International Conference on Computer Design and Engineering (ICCDE) (2011 ), 2011.
32. A. Jahanian, "Chip master planning an efficient methodology to improve design closure and complexity management of ultra large chips" , In CSI Internationa Symposium on Computer Architecture and Digital Systems(CADS), 2010.
33. M. N., A. Jahanian, A. Razavi, M. Saheb zamani, "A thermal-aware delay model for pass transistor in FPGA switch boxes" , 2010.
34. A. Jahanian, M. S., "Improved performance and yield whih chip master planingdesign methodology" , In GLSVLSI, 2009.
35. A. Jahanian, M. S., "Improved performance and yield with Chip Master planning design methodology" , In Great Lakes Symposium on VLSI (GLSVLSI) (2009 ), 2009.
36. A. Jahanian, M. Saheb zamani, "Improved timing closure by early buffer planning in floor-placement design flow" , In GLSVLSI, 2009.
37. A. S., A. Jahanian, S. Khalighi, "A light - weght car navigation algorithm for high speed agents using wireless landmarks" , In ICIA 2009 IEEE International Conference on Information and Automation, 2009.
38. N. Abdollahzadeh, M. M., A. Jahanian, M. S., "Multi -domain clock skew scheduling - Aware register placementto optimize clock distribution network" , In Date (design automation test in europe, 2009.
39. A. Dokhanchi, M. Rezvani, A. Jahanian, M. Saheb zamani, "Performance improvement of physical retiming with shortcut insertion" , In IEEE computer society annual symposium on VLSI, 2008.
40. A. Jahanian, "Performance and timing yield enhancement using Highway-on-Chip Planning" , In EuroMicro Digital System Design(DSD), 2008.
41. A. Jahanian, M. Saheb zamani, "Multi-level buffer block planning and buffer insertion for large design circuits" , In IEEE computer society annual symposium on VLSI, 2008.
42. A. Jahanian, "Buffer planning using the buffer requirement map with congestion control" , In The 13th CsI international computer conference (CSIC 2008), 2008.
43. A. Jahanian, "Using asynchronous serial transmission in physical design for congestion reduction" , In IEEE East-West Design and Test Conference, 2007.
44. A. Jahanian, "Buffer insertion during placement with floorplanning information" , In Csicc 2007, 2007.
45. A. Jahanian, "Prediction and reduction of routing congestion" , In International Symposium on Physical Design(ISPD), 2006.
46. A. Jahanian, "A hybrid heuristically and mathematically approach for VLSI standard cell placement" , In The 11the Computer Society of Iran Computer Conference (CSICC 2006), 2006.
47. A. Jahanian, "Feasibility of using component based software formal verification by hardware formal verification tools" , In The 11the Computer Society of Iran Computer Conference (CSICC 2006), 2006.
48. A. Jahanian, "An efficient congestion reduction algorithm based on contour plotting" , In International Conference on Microelectronics, 2005.
49. A. Jahanian, "Congestion prediction from metric definition to routing estimation" , In International Conference on Microelectronics, 2005.
50. A. Jahanian, "Efficient host-independent coprocessor architecture for speech coding algorithms" , In EuroMicro Digital System Design(DSD), 2005.
51. A. Jahanian, "Parallelizing the PathFinder Global Routing Algorithm using Multi-core Systems" , In The 19th Iranian Conference on Electrical Engineering, 2005.
52. A. Jahanian, "Using On-chip RF-Interconnects to Optimize Clock Distribution Network In 19th Iranian Conference on Electrical Engineering (ICEE)" , In The 19th Iranian Conference on Electrical Engineering, 2005.
53. A. Jahanian, "Area efficient low power and robust design for add-compare-select units" , In EuroMicro Digital System Design(DSD), 2004.
54. A. Jahanian, "Hardware-Software Co-Simulation" , 1999.
55. A. Omid, A. Jahanian, "A New Nano-scale Differential Logic Style for Power Analysis Attack" , 1992.
56. A. Jahanian, "Ant colony solution dynamic Steiner tree problem" , In The 7the Computer Society of Iran Computer Conference (CSICC 2002).
57. "ارائه الگوريتم افراز موازي و پياده سازي آن روي واحد پردازش گرافيكي" .
58. و. بريري, ع. جهانيان, "ارائه يك روش مقياس پذير براي طراحي مدارهاي ديجيتال چند طبقه مبتني بر DNA" اولين كنفرانس بين المللي دستاوردهاي نوين پژوهشي در مهندسي برق و كامپيوتر, 1395.
59. ب. احمدي حاجي, و. مهرشاد, ع. جهانيان, "بهبود ايمني حافظه هاي سامانه هاي نهفته در برابر حملات كانال جانبي توان با تكنيك متوازن سازي تعداد گذار" دوازدهمين كنفرانس بين المللي انجمن رمز ايران, 1394.
60. ش. زمان زاده, ع. جهانيان, "ارتقاي سطح امنيت مدارات مجتمع خاص منظوره در مقابل حملهي مهندسي معكوس در طول فرآيند ساخت، به وسيله رمز نمودن اتصالات داخل تراشه" دوازدهمين كنفرانس بين المللي انجمن رمز ايران, 1394.
61. ع. حداد, . مريم, ع. جهانيان, "ارائه يك معماري برنامه پذير جديد براي تراشه هاي زيستي ريز سيال ديجيتال" بيست و دومين كنفرانس مهندسي برق ايرانICEE2014, 1393.
62. م. جرنگي, ع. جهانيان, م. سام دليري, م. معيري, "ارائه يك كتابخانه صنعتي سلول هاي استاندارد براساس فناوري نانولوله هاي كربني" نوزدهمين كنفرانس ملي سالانه انجمن كامپيوتر ايران, 1392.
63. ع. زارعي, ع. جهانيان, "طرح ريزي اتصالات امواج راديويي روي مدارهاي مجتمع خاص منظوره با هدف بهبود كارايي" هجدهمين كنفرانس ملي سالانه انجمن كامپيوتر ايران, 1391.
64. م. وثوقي, ع. جهانيان, "جلوگيري از درج ويروس هاي سخت افزاري با ارائه يك معماري جديد براي درخت سيگنال ساعت" هجدهمين كنفرانس ملي سالانه انجمن كامپيوتر ايران, 1391.
65. ا. نيلوفر, ط. سمانه, ع. جهانيان, ن. حميد, "ارائه ي معماري و دستورات سفارشي جديد براي سفارشي سازي معماري پردازنده ي جاوا با هدف بهبود كارايي اين نوع پردازنده" بيستمين كنفرانس مهندسي برق ايرانICEE2012, 1391.
66. ع. پيشوايي, ق. جابري پور, ع. جهانيان, "طراحي كمپرسور (2 4 CMOS سريع بر پايه دروازه XOR سه ورودي" هفدهمين كنفرانس ملي سالانه انجمن كامپيوتر ايران, 1390.
67. ش. شهابي آهنگر كلايي, ع. جهانيان, "بهبود ساختار جعبه سوئيچ به منظور مقاوم سازي آرايه هاي دروازه اي برنامه پذير در برابر مهندسي معكوس رشته بيتي" كنفرانس مهندسي برق ايران, 1371.


Shahid Beheshti University

Shahid Beheshti University